/**
 * \file IfxSdmmc_bf.h
 * \brief
 * \copyright Copyright (c) 2020 Infineon Technologies AG. All rights reserved.
 *
 *
 * Version: TC39XB_UM_V1.5.0
 * Specification: TC3xx User Manual V1.5.0
 * MAY BE CHANGED BY USER [yes/no]: No
 *
 *                                 IMPORTANT NOTICE
 *
 * Use of this file is subject to the terms of use agreed between (i) you or
 * the company in which ordinary course of business you are acting and (ii)
 * Infineon Technologies AG or its licensees. If and as long as no such terms
 * of use are agreed, use of this file is subject to following:
 *
 * Boost Software License - Version 1.0 - August 17th, 2003
 *
 * Permission is hereby granted, free of charge, to any person or organization
 * obtaining a copy of the software and accompanying documentation covered by
 * this license (the "Software") to use, reproduce, display, distribute,
 * execute, and transmit the Software, and to prepare derivative works of the
 * Software, and to permit third-parties to whom the Software is furnished to
 * do so, all subject to the following:
 *
 * The copyright notices in the Software and this entire statement, including
 * the above license grant, this restriction and the following disclaimer, must
 * be included in all copies of the Software, in whole or in part, and all
 * derivative works of the Software, unless such copies or derivative works are
 * solely in the form of machine-executable object code generated by a source
 * language processor.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
 * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
 * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * \defgroup IfxSfr_Sdmmc_Registers_BitfieldsMask Bitfields mask and offset
 * \ingroup IfxSfr_Sdmmc_Registers
 * 
 */
#ifndef IFXSDMMC_BF_H
#define IFXSDMMC_BF_H 1

/******************************************************************************/

/******************************************************************************/

/** \addtogroup IfxSfr_Sdmmc_Registers_BitfieldsMask
 * \{  */
/** \brief Length for Ifx_SDMMC_SDMASA_Bits.BLOCKCNT_SDMASA */
#define IFX_SDMMC_SDMASA_BLOCKCNT_SDMASA_LEN (32u)

/** \brief Mask for Ifx_SDMMC_SDMASA_Bits.BLOCKCNT_SDMASA */
#define IFX_SDMMC_SDMASA_BLOCKCNT_SDMASA_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_SDMASA_Bits.BLOCKCNT_SDMASA */
#define IFX_SDMMC_SDMASA_BLOCKCNT_SDMASA_OFF (0u)

/** \brief Length for Ifx_SDMMC_BLOCKSIZE_Bits.XFER_BLOCK_SIZE */
#define IFX_SDMMC_BLOCKSIZE_XFER_BLOCK_SIZE_LEN (12u)

/** \brief Mask for Ifx_SDMMC_BLOCKSIZE_Bits.XFER_BLOCK_SIZE */
#define IFX_SDMMC_BLOCKSIZE_XFER_BLOCK_SIZE_MSK (0xfffu)

/** \brief Offset for Ifx_SDMMC_BLOCKSIZE_Bits.XFER_BLOCK_SIZE */
#define IFX_SDMMC_BLOCKSIZE_XFER_BLOCK_SIZE_OFF (0u)

/** \brief Length for Ifx_SDMMC_BLOCKSIZE_Bits.SDMA_BUF_BDARY */
#define IFX_SDMMC_BLOCKSIZE_SDMA_BUF_BDARY_LEN (3u)

/** \brief Mask for Ifx_SDMMC_BLOCKSIZE_Bits.SDMA_BUF_BDARY */
#define IFX_SDMMC_BLOCKSIZE_SDMA_BUF_BDARY_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_BLOCKSIZE_Bits.SDMA_BUF_BDARY */
#define IFX_SDMMC_BLOCKSIZE_SDMA_BUF_BDARY_OFF (12u)

/** \brief Length for Ifx_SDMMC_BLOCKCOUNT_Bits.BLOCK_CNT */
#define IFX_SDMMC_BLOCKCOUNT_BLOCK_CNT_LEN (16u)

/** \brief Mask for Ifx_SDMMC_BLOCKCOUNT_Bits.BLOCK_CNT */
#define IFX_SDMMC_BLOCKCOUNT_BLOCK_CNT_MSK (0xffffu)

/** \brief Offset for Ifx_SDMMC_BLOCKCOUNT_Bits.BLOCK_CNT */
#define IFX_SDMMC_BLOCKCOUNT_BLOCK_CNT_OFF (0u)

/** \brief Length for Ifx_SDMMC_ARGUMENT_Bits.ARGUMENT */
#define IFX_SDMMC_ARGUMENT_ARGUMENT_LEN (32u)

/** \brief Mask for Ifx_SDMMC_ARGUMENT_Bits.ARGUMENT */
#define IFX_SDMMC_ARGUMENT_ARGUMENT_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_ARGUMENT_Bits.ARGUMENT */
#define IFX_SDMMC_ARGUMENT_ARGUMENT_OFF (0u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.DMA_ENABLE */
#define IFX_SDMMC_XFER_MODE_DMA_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.DMA_ENABLE */
#define IFX_SDMMC_XFER_MODE_DMA_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.DMA_ENABLE */
#define IFX_SDMMC_XFER_MODE_DMA_ENABLE_OFF (0u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.BLOCK_COUNT_ENABLE */
#define IFX_SDMMC_XFER_MODE_BLOCK_COUNT_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.BLOCK_COUNT_ENABLE */
#define IFX_SDMMC_XFER_MODE_BLOCK_COUNT_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.BLOCK_COUNT_ENABLE */
#define IFX_SDMMC_XFER_MODE_BLOCK_COUNT_ENABLE_OFF (1u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.AUTO_CMD_ENABLE */
#define IFX_SDMMC_XFER_MODE_AUTO_CMD_ENABLE_LEN (2u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.AUTO_CMD_ENABLE */
#define IFX_SDMMC_XFER_MODE_AUTO_CMD_ENABLE_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.AUTO_CMD_ENABLE */
#define IFX_SDMMC_XFER_MODE_AUTO_CMD_ENABLE_OFF (2u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.DATA_XFER_DIR */
#define IFX_SDMMC_XFER_MODE_DATA_XFER_DIR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.DATA_XFER_DIR */
#define IFX_SDMMC_XFER_MODE_DATA_XFER_DIR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.DATA_XFER_DIR */
#define IFX_SDMMC_XFER_MODE_DATA_XFER_DIR_OFF (4u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.MULTI_BLK_SEL */
#define IFX_SDMMC_XFER_MODE_MULTI_BLK_SEL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.MULTI_BLK_SEL */
#define IFX_SDMMC_XFER_MODE_MULTI_BLK_SEL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.MULTI_BLK_SEL */
#define IFX_SDMMC_XFER_MODE_MULTI_BLK_SEL_OFF (5u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.RESP_TYPE */
#define IFX_SDMMC_XFER_MODE_RESP_TYPE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.RESP_TYPE */
#define IFX_SDMMC_XFER_MODE_RESP_TYPE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.RESP_TYPE */
#define IFX_SDMMC_XFER_MODE_RESP_TYPE_OFF (6u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.RESP_ERR_CHK_ENABLE */
#define IFX_SDMMC_XFER_MODE_RESP_ERR_CHK_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.RESP_ERR_CHK_ENABLE */
#define IFX_SDMMC_XFER_MODE_RESP_ERR_CHK_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.RESP_ERR_CHK_ENABLE */
#define IFX_SDMMC_XFER_MODE_RESP_ERR_CHK_ENABLE_OFF (7u)

/** \brief Length for Ifx_SDMMC_XFER_MODE_Bits.RESP_INT_DISABLE */
#define IFX_SDMMC_XFER_MODE_RESP_INT_DISABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_XFER_MODE_Bits.RESP_INT_DISABLE */
#define IFX_SDMMC_XFER_MODE_RESP_INT_DISABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_XFER_MODE_Bits.RESP_INT_DISABLE */
#define IFX_SDMMC_XFER_MODE_RESP_INT_DISABLE_OFF (8u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.RESP_TYPE_SELECT */
#define IFX_SDMMC_CMD_RESP_TYPE_SELECT_LEN (2u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.RESP_TYPE_SELECT */
#define IFX_SDMMC_CMD_RESP_TYPE_SELECT_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.RESP_TYPE_SELECT */
#define IFX_SDMMC_CMD_RESP_TYPE_SELECT_OFF (0u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.SUB_CMD_FLAG */
#define IFX_SDMMC_CMD_SUB_CMD_FLAG_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.SUB_CMD_FLAG */
#define IFX_SDMMC_CMD_SUB_CMD_FLAG_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.SUB_CMD_FLAG */
#define IFX_SDMMC_CMD_SUB_CMD_FLAG_OFF (2u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.CMD_CRC_CHK_ENABLE */
#define IFX_SDMMC_CMD_CMD_CRC_CHK_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.CMD_CRC_CHK_ENABLE */
#define IFX_SDMMC_CMD_CMD_CRC_CHK_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.CMD_CRC_CHK_ENABLE */
#define IFX_SDMMC_CMD_CMD_CRC_CHK_ENABLE_OFF (3u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.CMD_IDX_CHK_ENABLE */
#define IFX_SDMMC_CMD_CMD_IDX_CHK_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.CMD_IDX_CHK_ENABLE */
#define IFX_SDMMC_CMD_CMD_IDX_CHK_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.CMD_IDX_CHK_ENABLE */
#define IFX_SDMMC_CMD_CMD_IDX_CHK_ENABLE_OFF (4u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.DATA_PRESENT_SEL */
#define IFX_SDMMC_CMD_DATA_PRESENT_SEL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.DATA_PRESENT_SEL */
#define IFX_SDMMC_CMD_DATA_PRESENT_SEL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.DATA_PRESENT_SEL */
#define IFX_SDMMC_CMD_DATA_PRESENT_SEL_OFF (5u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.CMD_TYPE */
#define IFX_SDMMC_CMD_CMD_TYPE_LEN (2u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.CMD_TYPE */
#define IFX_SDMMC_CMD_CMD_TYPE_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.CMD_TYPE */
#define IFX_SDMMC_CMD_CMD_TYPE_OFF (6u)

/** \brief Length for Ifx_SDMMC_CMD_Bits.CMD_INDEX */
#define IFX_SDMMC_CMD_CMD_INDEX_LEN (6u)

/** \brief Mask for Ifx_SDMMC_CMD_Bits.CMD_INDEX */
#define IFX_SDMMC_CMD_CMD_INDEX_MSK (0x3fu)

/** \brief Offset for Ifx_SDMMC_CMD_Bits.CMD_INDEX */
#define IFX_SDMMC_CMD_CMD_INDEX_OFF (8u)

/** \brief Length for Ifx_SDMMC_RESP01_Bits.RESP01 */
#define IFX_SDMMC_RESP01_RESP01_LEN (32u)

/** \brief Mask for Ifx_SDMMC_RESP01_Bits.RESP01 */
#define IFX_SDMMC_RESP01_RESP01_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_RESP01_Bits.RESP01 */
#define IFX_SDMMC_RESP01_RESP01_OFF (0u)

/** \brief Length for Ifx_SDMMC_RESP23_Bits.RESP23 */
#define IFX_SDMMC_RESP23_RESP23_LEN (32u)

/** \brief Mask for Ifx_SDMMC_RESP23_Bits.RESP23 */
#define IFX_SDMMC_RESP23_RESP23_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_RESP23_Bits.RESP23 */
#define IFX_SDMMC_RESP23_RESP23_OFF (0u)

/** \brief Length for Ifx_SDMMC_RESP45_Bits.RESP45 */
#define IFX_SDMMC_RESP45_RESP45_LEN (32u)

/** \brief Mask for Ifx_SDMMC_RESP45_Bits.RESP45 */
#define IFX_SDMMC_RESP45_RESP45_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_RESP45_Bits.RESP45 */
#define IFX_SDMMC_RESP45_RESP45_OFF (0u)

/** \brief Length for Ifx_SDMMC_RESP67_Bits.RESP67 */
#define IFX_SDMMC_RESP67_RESP67_LEN (32u)

/** \brief Mask for Ifx_SDMMC_RESP67_Bits.RESP67 */
#define IFX_SDMMC_RESP67_RESP67_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_RESP67_Bits.RESP67 */
#define IFX_SDMMC_RESP67_RESP67_OFF (0u)

/** \brief Length for Ifx_SDMMC_BUF_DATA_Bits.BUF_DATA */
#define IFX_SDMMC_BUF_DATA_BUF_DATA_LEN (32u)

/** \brief Mask for Ifx_SDMMC_BUF_DATA_Bits.BUF_DATA */
#define IFX_SDMMC_BUF_DATA_BUF_DATA_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_BUF_DATA_Bits.BUF_DATA */
#define IFX_SDMMC_BUF_DATA_BUF_DATA_OFF (0u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CMD_INHIBIT */
#define IFX_SDMMC_PSTATE_REG_CMD_INHIBIT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CMD_INHIBIT */
#define IFX_SDMMC_PSTATE_REG_CMD_INHIBIT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CMD_INHIBIT */
#define IFX_SDMMC_PSTATE_REG_CMD_INHIBIT_OFF (0u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CMD_INHIBIT_DAT */
#define IFX_SDMMC_PSTATE_REG_CMD_INHIBIT_DAT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CMD_INHIBIT_DAT */
#define IFX_SDMMC_PSTATE_REG_CMD_INHIBIT_DAT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CMD_INHIBIT_DAT */
#define IFX_SDMMC_PSTATE_REG_CMD_INHIBIT_DAT_OFF (1u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.DAT_LINE_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_DAT_LINE_ACTIVE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.DAT_LINE_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_DAT_LINE_ACTIVE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.DAT_LINE_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_DAT_LINE_ACTIVE_OFF (2u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.RE_TUNE_REQ */
#define IFX_SDMMC_PSTATE_REG_RE_TUNE_REQ_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.RE_TUNE_REQ */
#define IFX_SDMMC_PSTATE_REG_RE_TUNE_REQ_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.RE_TUNE_REQ */
#define IFX_SDMMC_PSTATE_REG_RE_TUNE_REQ_OFF (3u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.DAT_7_4 */
#define IFX_SDMMC_PSTATE_REG_DAT_7_4_LEN (4u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.DAT_7_4 */
#define IFX_SDMMC_PSTATE_REG_DAT_7_4_MSK (0xfu)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.DAT_7_4 */
#define IFX_SDMMC_PSTATE_REG_DAT_7_4_OFF (4u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.WR_XFER_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_WR_XFER_ACTIVE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.WR_XFER_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_WR_XFER_ACTIVE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.WR_XFER_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_WR_XFER_ACTIVE_OFF (8u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.RD_XFER_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_RD_XFER_ACTIVE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.RD_XFER_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_RD_XFER_ACTIVE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.RD_XFER_ACTIVE */
#define IFX_SDMMC_PSTATE_REG_RD_XFER_ACTIVE_OFF (9u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.BUF_WR_ENABLE */
#define IFX_SDMMC_PSTATE_REG_BUF_WR_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.BUF_WR_ENABLE */
#define IFX_SDMMC_PSTATE_REG_BUF_WR_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.BUF_WR_ENABLE */
#define IFX_SDMMC_PSTATE_REG_BUF_WR_ENABLE_OFF (10u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.BUF_RD_ENABLE */
#define IFX_SDMMC_PSTATE_REG_BUF_RD_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.BUF_RD_ENABLE */
#define IFX_SDMMC_PSTATE_REG_BUF_RD_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.BUF_RD_ENABLE */
#define IFX_SDMMC_PSTATE_REG_BUF_RD_ENABLE_OFF (11u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CARD_INSERTED */
#define IFX_SDMMC_PSTATE_REG_CARD_INSERTED_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CARD_INSERTED */
#define IFX_SDMMC_PSTATE_REG_CARD_INSERTED_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CARD_INSERTED */
#define IFX_SDMMC_PSTATE_REG_CARD_INSERTED_OFF (16u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CARD_STABLE */
#define IFX_SDMMC_PSTATE_REG_CARD_STABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CARD_STABLE */
#define IFX_SDMMC_PSTATE_REG_CARD_STABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CARD_STABLE */
#define IFX_SDMMC_PSTATE_REG_CARD_STABLE_OFF (17u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CARD_DETECT_LEVEL */
#define IFX_SDMMC_PSTATE_REG_CARD_DETECT_LEVEL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CARD_DETECT_LEVEL */
#define IFX_SDMMC_PSTATE_REG_CARD_DETECT_LEVEL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CARD_DETECT_LEVEL */
#define IFX_SDMMC_PSTATE_REG_CARD_DETECT_LEVEL_OFF (18u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.WR_PROTECT_SW_LVL */
#define IFX_SDMMC_PSTATE_REG_WR_PROTECT_SW_LVL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.WR_PROTECT_SW_LVL */
#define IFX_SDMMC_PSTATE_REG_WR_PROTECT_SW_LVL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.WR_PROTECT_SW_LVL */
#define IFX_SDMMC_PSTATE_REG_WR_PROTECT_SW_LVL_OFF (19u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.DAT_3_0 */
#define IFX_SDMMC_PSTATE_REG_DAT_3_0_LEN (4u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.DAT_3_0 */
#define IFX_SDMMC_PSTATE_REG_DAT_3_0_MSK (0xfu)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.DAT_3_0 */
#define IFX_SDMMC_PSTATE_REG_DAT_3_0_OFF (20u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CMD_LINE_LVL */
#define IFX_SDMMC_PSTATE_REG_CMD_LINE_LVL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CMD_LINE_LVL */
#define IFX_SDMMC_PSTATE_REG_CMD_LINE_LVL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CMD_LINE_LVL */
#define IFX_SDMMC_PSTATE_REG_CMD_LINE_LVL_OFF (24u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.HOST_REG_VOL */
#define IFX_SDMMC_PSTATE_REG_HOST_REG_VOL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.HOST_REG_VOL */
#define IFX_SDMMC_PSTATE_REG_HOST_REG_VOL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.HOST_REG_VOL */
#define IFX_SDMMC_PSTATE_REG_HOST_REG_VOL_OFF (25u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.CMD_ISSUE_ERR */
#define IFX_SDMMC_PSTATE_REG_CMD_ISSUE_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.CMD_ISSUE_ERR */
#define IFX_SDMMC_PSTATE_REG_CMD_ISSUE_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.CMD_ISSUE_ERR */
#define IFX_SDMMC_PSTATE_REG_CMD_ISSUE_ERR_OFF (27u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.SUB_CMD_STAT */
#define IFX_SDMMC_PSTATE_REG_SUB_CMD_STAT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.SUB_CMD_STAT */
#define IFX_SDMMC_PSTATE_REG_SUB_CMD_STAT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.SUB_CMD_STAT */
#define IFX_SDMMC_PSTATE_REG_SUB_CMD_STAT_OFF (28u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.IN_DORMANT_ST */
#define IFX_SDMMC_PSTATE_REG_IN_DORMANT_ST_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.IN_DORMANT_ST */
#define IFX_SDMMC_PSTATE_REG_IN_DORMANT_ST_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.IN_DORMANT_ST */
#define IFX_SDMMC_PSTATE_REG_IN_DORMANT_ST_OFF (29u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.LANE_SYNC */
#define IFX_SDMMC_PSTATE_REG_LANE_SYNC_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.LANE_SYNC */
#define IFX_SDMMC_PSTATE_REG_LANE_SYNC_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.LANE_SYNC */
#define IFX_SDMMC_PSTATE_REG_LANE_SYNC_OFF (30u)

/** \brief Length for Ifx_SDMMC_PSTATE_REG_Bits.UHS2_IF_DETECT */
#define IFX_SDMMC_PSTATE_REG_UHS2_IF_DETECT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PSTATE_REG_Bits.UHS2_IF_DETECT */
#define IFX_SDMMC_PSTATE_REG_UHS2_IF_DETECT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PSTATE_REG_Bits.UHS2_IF_DETECT */
#define IFX_SDMMC_PSTATE_REG_UHS2_IF_DETECT_OFF (31u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.LED_CTRL */
#define IFX_SDMMC_HOST_CTRL1_LED_CTRL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.LED_CTRL */
#define IFX_SDMMC_HOST_CTRL1_LED_CTRL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.LED_CTRL */
#define IFX_SDMMC_HOST_CTRL1_LED_CTRL_OFF (0u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.DAT_XFER_WIDTH */
#define IFX_SDMMC_HOST_CTRL1_DAT_XFER_WIDTH_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.DAT_XFER_WIDTH */
#define IFX_SDMMC_HOST_CTRL1_DAT_XFER_WIDTH_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.DAT_XFER_WIDTH */
#define IFX_SDMMC_HOST_CTRL1_DAT_XFER_WIDTH_OFF (1u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.HIGH_SPEED_EN */
#define IFX_SDMMC_HOST_CTRL1_HIGH_SPEED_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.HIGH_SPEED_EN */
#define IFX_SDMMC_HOST_CTRL1_HIGH_SPEED_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.HIGH_SPEED_EN */
#define IFX_SDMMC_HOST_CTRL1_HIGH_SPEED_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.DMA_SEL */
#define IFX_SDMMC_HOST_CTRL1_DMA_SEL_LEN (2u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.DMA_SEL */
#define IFX_SDMMC_HOST_CTRL1_DMA_SEL_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.DMA_SEL */
#define IFX_SDMMC_HOST_CTRL1_DMA_SEL_OFF (3u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.EXT_DAT_XFER */
#define IFX_SDMMC_HOST_CTRL1_EXT_DAT_XFER_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.EXT_DAT_XFER */
#define IFX_SDMMC_HOST_CTRL1_EXT_DAT_XFER_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.EXT_DAT_XFER */
#define IFX_SDMMC_HOST_CTRL1_EXT_DAT_XFER_OFF (5u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.CARD_DETECT_TEST_LVL */
#define IFX_SDMMC_HOST_CTRL1_CARD_DETECT_TEST_LVL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.CARD_DETECT_TEST_LVL */
#define IFX_SDMMC_HOST_CTRL1_CARD_DETECT_TEST_LVL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.CARD_DETECT_TEST_LVL */
#define IFX_SDMMC_HOST_CTRL1_CARD_DETECT_TEST_LVL_OFF (6u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL1_Bits.CARD_DETECT_SIG_LVL */
#define IFX_SDMMC_HOST_CTRL1_CARD_DETECT_SIG_LVL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL1_Bits.CARD_DETECT_SIG_LVL */
#define IFX_SDMMC_HOST_CTRL1_CARD_DETECT_SIG_LVL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL1_Bits.CARD_DETECT_SIG_LVL */
#define IFX_SDMMC_HOST_CTRL1_CARD_DETECT_SIG_LVL_OFF (7u)

/** \brief Length for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_PWR_VDD1 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_PWR_VDD1_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_PWR_VDD1 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_PWR_VDD1_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_PWR_VDD1 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_PWR_VDD1_OFF (0u)

/** \brief Length for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_VOL_VDD1 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_VOL_VDD1_LEN (3u)

/** \brief Mask for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_VOL_VDD1 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_VOL_VDD1_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_VOL_VDD1 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_VOL_VDD1_OFF (1u)

/** \brief Length for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_PWR_VDD2 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_PWR_VDD2_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_PWR_VDD2 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_PWR_VDD2_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_PWR_VDD2 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_PWR_VDD2_OFF (4u)

/** \brief Length for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_VOL_VDD2 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_VOL_VDD2_LEN (3u)

/** \brief Mask for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_VOL_VDD2 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_VOL_VDD2_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_PWR_CTRL_Bits.SD_BUS_VOL_VDD2 */
#define IFX_SDMMC_PWR_CTRL_SD_BUS_VOL_VDD2_OFF (5u)

/** \brief Length for Ifx_SDMMC_BGAP_CTRL_Bits.STOP_BG_REQ */
#define IFX_SDMMC_BGAP_CTRL_STOP_BG_REQ_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BGAP_CTRL_Bits.STOP_BG_REQ */
#define IFX_SDMMC_BGAP_CTRL_STOP_BG_REQ_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BGAP_CTRL_Bits.STOP_BG_REQ */
#define IFX_SDMMC_BGAP_CTRL_STOP_BG_REQ_OFF (0u)

/** \brief Length for Ifx_SDMMC_BGAP_CTRL_Bits.CONTINUE_REQ */
#define IFX_SDMMC_BGAP_CTRL_CONTINUE_REQ_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BGAP_CTRL_Bits.CONTINUE_REQ */
#define IFX_SDMMC_BGAP_CTRL_CONTINUE_REQ_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BGAP_CTRL_Bits.CONTINUE_REQ */
#define IFX_SDMMC_BGAP_CTRL_CONTINUE_REQ_OFF (1u)

/** \brief Length for Ifx_SDMMC_BGAP_CTRL_Bits.RD_WAIT_CTRL */
#define IFX_SDMMC_BGAP_CTRL_RD_WAIT_CTRL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BGAP_CTRL_Bits.RD_WAIT_CTRL */
#define IFX_SDMMC_BGAP_CTRL_RD_WAIT_CTRL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BGAP_CTRL_Bits.RD_WAIT_CTRL */
#define IFX_SDMMC_BGAP_CTRL_RD_WAIT_CTRL_OFF (2u)

/** \brief Length for Ifx_SDMMC_BGAP_CTRL_Bits.INT_AT_BGAP */
#define IFX_SDMMC_BGAP_CTRL_INT_AT_BGAP_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BGAP_CTRL_Bits.INT_AT_BGAP */
#define IFX_SDMMC_BGAP_CTRL_INT_AT_BGAP_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BGAP_CTRL_Bits.INT_AT_BGAP */
#define IFX_SDMMC_BGAP_CTRL_INT_AT_BGAP_OFF (3u)

/** \brief Length for Ifx_SDMMC_WUP_CTRL_Bits.CARD_INT */
#define IFX_SDMMC_WUP_CTRL_CARD_INT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_WUP_CTRL_Bits.CARD_INT */
#define IFX_SDMMC_WUP_CTRL_CARD_INT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_WUP_CTRL_Bits.CARD_INT */
#define IFX_SDMMC_WUP_CTRL_CARD_INT_OFF (0u)

/** \brief Length for Ifx_SDMMC_WUP_CTRL_Bits.CARD_INSERT */
#define IFX_SDMMC_WUP_CTRL_CARD_INSERT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_WUP_CTRL_Bits.CARD_INSERT */
#define IFX_SDMMC_WUP_CTRL_CARD_INSERT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_WUP_CTRL_Bits.CARD_INSERT */
#define IFX_SDMMC_WUP_CTRL_CARD_INSERT_OFF (1u)

/** \brief Length for Ifx_SDMMC_WUP_CTRL_Bits.CARD_REMOVAL */
#define IFX_SDMMC_WUP_CTRL_CARD_REMOVAL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_WUP_CTRL_Bits.CARD_REMOVAL */
#define IFX_SDMMC_WUP_CTRL_CARD_REMOVAL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_WUP_CTRL_Bits.CARD_REMOVAL */
#define IFX_SDMMC_WUP_CTRL_CARD_REMOVAL_OFF (2u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.INTERNAL_CLK_EN */
#define IFX_SDMMC_CLK_CTRL_INTERNAL_CLK_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.INTERNAL_CLK_EN */
#define IFX_SDMMC_CLK_CTRL_INTERNAL_CLK_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.INTERNAL_CLK_EN */
#define IFX_SDMMC_CLK_CTRL_INTERNAL_CLK_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.INTERNAL_CLK_STABLE */
#define IFX_SDMMC_CLK_CTRL_INTERNAL_CLK_STABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.INTERNAL_CLK_STABLE */
#define IFX_SDMMC_CLK_CTRL_INTERNAL_CLK_STABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.INTERNAL_CLK_STABLE */
#define IFX_SDMMC_CLK_CTRL_INTERNAL_CLK_STABLE_OFF (1u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.SD_CLK_EN */
#define IFX_SDMMC_CLK_CTRL_SD_CLK_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.SD_CLK_EN */
#define IFX_SDMMC_CLK_CTRL_SD_CLK_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.SD_CLK_EN */
#define IFX_SDMMC_CLK_CTRL_SD_CLK_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.PLL_ENABLE */
#define IFX_SDMMC_CLK_CTRL_PLL_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.PLL_ENABLE */
#define IFX_SDMMC_CLK_CTRL_PLL_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.PLL_ENABLE */
#define IFX_SDMMC_CLK_CTRL_PLL_ENABLE_OFF (3u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.CLK_GEN_SELECT */
#define IFX_SDMMC_CLK_CTRL_CLK_GEN_SELECT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.CLK_GEN_SELECT */
#define IFX_SDMMC_CLK_CTRL_CLK_GEN_SELECT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.CLK_GEN_SELECT */
#define IFX_SDMMC_CLK_CTRL_CLK_GEN_SELECT_OFF (5u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.UPPER_FREQ_SEL */
#define IFX_SDMMC_CLK_CTRL_UPPER_FREQ_SEL_LEN (2u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.UPPER_FREQ_SEL */
#define IFX_SDMMC_CLK_CTRL_UPPER_FREQ_SEL_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.UPPER_FREQ_SEL */
#define IFX_SDMMC_CLK_CTRL_UPPER_FREQ_SEL_OFF (6u)

/** \brief Length for Ifx_SDMMC_CLK_CTRL_Bits.FREQ_SEL */
#define IFX_SDMMC_CLK_CTRL_FREQ_SEL_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CLK_CTRL_Bits.FREQ_SEL */
#define IFX_SDMMC_CLK_CTRL_FREQ_SEL_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CLK_CTRL_Bits.FREQ_SEL */
#define IFX_SDMMC_CLK_CTRL_FREQ_SEL_OFF (8u)

/** \brief Length for Ifx_SDMMC_TOUT_CTRL_Bits.TOUT_CNT */
#define IFX_SDMMC_TOUT_CTRL_TOUT_CNT_LEN (4u)

/** \brief Mask for Ifx_SDMMC_TOUT_CTRL_Bits.TOUT_CNT */
#define IFX_SDMMC_TOUT_CTRL_TOUT_CNT_MSK (0xfu)

/** \brief Offset for Ifx_SDMMC_TOUT_CTRL_Bits.TOUT_CNT */
#define IFX_SDMMC_TOUT_CTRL_TOUT_CNT_OFF (0u)

/** \brief Length for Ifx_SDMMC_SW_RST_Bits.SW_RST_ALL */
#define IFX_SDMMC_SW_RST_SW_RST_ALL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_SW_RST_Bits.SW_RST_ALL */
#define IFX_SDMMC_SW_RST_SW_RST_ALL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_SW_RST_Bits.SW_RST_ALL */
#define IFX_SDMMC_SW_RST_SW_RST_ALL_OFF (0u)

/** \brief Length for Ifx_SDMMC_SW_RST_Bits.SW_RST_CMD */
#define IFX_SDMMC_SW_RST_SW_RST_CMD_LEN (1u)

/** \brief Mask for Ifx_SDMMC_SW_RST_Bits.SW_RST_CMD */
#define IFX_SDMMC_SW_RST_SW_RST_CMD_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_SW_RST_Bits.SW_RST_CMD */
#define IFX_SDMMC_SW_RST_SW_RST_CMD_OFF (1u)

/** \brief Length for Ifx_SDMMC_SW_RST_Bits.SW_RST_DAT */
#define IFX_SDMMC_SW_RST_SW_RST_DAT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_SW_RST_Bits.SW_RST_DAT */
#define IFX_SDMMC_SW_RST_SW_RST_DAT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_SW_RST_Bits.SW_RST_DAT */
#define IFX_SDMMC_SW_RST_SW_RST_DAT_OFF (2u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CMD_COMPLETE */
#define IFX_SDMMC_NORMAL_INT_STAT_CMD_COMPLETE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CMD_COMPLETE */
#define IFX_SDMMC_NORMAL_INT_STAT_CMD_COMPLETE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CMD_COMPLETE */
#define IFX_SDMMC_NORMAL_INT_STAT_CMD_COMPLETE_OFF (0u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.XFER_COMPLETE */
#define IFX_SDMMC_NORMAL_INT_STAT_XFER_COMPLETE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.XFER_COMPLETE */
#define IFX_SDMMC_NORMAL_INT_STAT_XFER_COMPLETE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.XFER_COMPLETE */
#define IFX_SDMMC_NORMAL_INT_STAT_XFER_COMPLETE_OFF (1u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BGAP_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_BGAP_EVENT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BGAP_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_BGAP_EVENT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BGAP_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_BGAP_EVENT_OFF (2u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.DMA_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_DMA_INTERRUPT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.DMA_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_DMA_INTERRUPT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.DMA_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_DMA_INTERRUPT_OFF (3u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BUF_WR_READY */
#define IFX_SDMMC_NORMAL_INT_STAT_BUF_WR_READY_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BUF_WR_READY */
#define IFX_SDMMC_NORMAL_INT_STAT_BUF_WR_READY_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BUF_WR_READY */
#define IFX_SDMMC_NORMAL_INT_STAT_BUF_WR_READY_OFF (4u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BUF_RD_READY */
#define IFX_SDMMC_NORMAL_INT_STAT_BUF_RD_READY_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BUF_RD_READY */
#define IFX_SDMMC_NORMAL_INT_STAT_BUF_RD_READY_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.BUF_RD_READY */
#define IFX_SDMMC_NORMAL_INT_STAT_BUF_RD_READY_OFF (5u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_INSERTION */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_INSERTION_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_INSERTION */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_INSERTION_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_INSERTION */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_INSERTION_OFF (6u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_REMOVAL */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_REMOVAL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_REMOVAL */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_REMOVAL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_REMOVAL */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_REMOVAL_OFF (7u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_INTERRUPT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_INTERRUPT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CARD_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_CARD_INTERRUPT_OFF (8u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_A */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_A_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_A */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_A_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_A */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_A_OFF (9u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_B */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_B_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_B */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_B_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_B */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_B_OFF (10u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_C */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_C_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_C */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_C_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.INT_C */
#define IFX_SDMMC_NORMAL_INT_STAT_INT_C_OFF (11u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.RE_TUNE_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_RE_TUNE_EVENT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.RE_TUNE_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_RE_TUNE_EVENT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.RE_TUNE_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_RE_TUNE_EVENT_OFF (12u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.FX_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_FX_EVENT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.FX_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_FX_EVENT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.FX_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_FX_EVENT_OFF (13u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CQE_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_CQE_EVENT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CQE_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_CQE_EVENT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.CQE_EVENT */
#define IFX_SDMMC_NORMAL_INT_STAT_CQE_EVENT_OFF (14u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_Bits.ERR_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_ERR_INTERRUPT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_Bits.ERR_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_ERR_INTERRUPT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_Bits.ERR_INTERRUPT */
#define IFX_SDMMC_NORMAL_INT_STAT_ERR_INTERRUPT_OFF (15u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_TOUT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_TOUT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_TOUT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_TOUT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_TOUT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_TOUT_ERR_OFF (0u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_CRC_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_CRC_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_CRC_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_CRC_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_CRC_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_CRC_ERR_OFF (1u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_END_BIT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_END_BIT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_END_BIT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_END_BIT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_END_BIT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_END_BIT_ERR_OFF (2u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_IDX_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_IDX_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_IDX_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_IDX_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.CMD_IDX_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CMD_IDX_ERR_OFF (3u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_TOUT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_TOUT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_TOUT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_TOUT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_TOUT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_TOUT_ERR_OFF (4u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_CRC_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_CRC_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_CRC_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_CRC_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_CRC_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_CRC_ERR_OFF (5u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_END_BIT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_END_BIT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_END_BIT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_END_BIT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.DATA_END_BIT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_DATA_END_BIT_ERR_OFF (6u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.CUR_LMT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CUR_LMT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.CUR_LMT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CUR_LMT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.CUR_LMT_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_CUR_LMT_ERR_OFF (7u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.AUTO_CMD_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_AUTO_CMD_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.AUTO_CMD_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_AUTO_CMD_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.AUTO_CMD_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_AUTO_CMD_ERR_OFF (8u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.ADMA_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_ADMA_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.ADMA_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_ADMA_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.ADMA_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_ADMA_ERR_OFF (9u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.TUNING_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_TUNING_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.TUNING_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_TUNING_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.TUNING_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_TUNING_ERR_OFF (10u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.RESP_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_RESP_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.RESP_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_RESP_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.RESP_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_RESP_ERR_OFF (11u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_Bits.BOOT_ACK_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_BOOT_ACK_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_Bits.BOOT_ACK_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_BOOT_ACK_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_Bits.BOOT_ACK_ERR */
#define IFX_SDMMC_ERROR_INT_STAT_BOOT_ACK_ERR_OFF (12u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CMD_COMPLETE_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CMD_COMPLETE_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CMD_COMPLETE_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CMD_COMPLETE_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CMD_COMPLETE_STAT_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.XFER_COMPLETE_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_XFER_COMPLETE_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.XFER_COMPLETE_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.XFER_COMPLETE_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_XFER_COMPLETE_STAT_EN_OFF (1u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BGAP_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BGAP_EVENT_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BGAP_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BGAP_EVENT_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BGAP_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BGAP_EVENT_STAT_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.DMA_INTERRUPT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.DMA_INTERRUPT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.DMA_INTERRUPT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_OFF (3u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BUF_WR_READY_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BUF_WR_READY_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BUF_WR_READY_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BUF_WR_READY_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BUF_WR_READY_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BUF_WR_READY_STAT_EN_OFF (4u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BUF_RD_READY_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BUF_RD_READY_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BUF_RD_READY_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BUF_RD_READY_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.BUF_RD_READY_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_BUF_RD_READY_STAT_EN_OFF (5u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_INSERTION_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_INSERTION_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_INSERTION_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_INSERTION_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_INSERTION_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_INSERTION_STAT_EN_OFF (6u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_REMOVAL_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_REMOVAL_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_REMOVAL_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_REMOVAL_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_REMOVAL_STAT_EN_OFF (7u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_INTERRUPT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_INTERRUPT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CARD_INTERRUPT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_OFF (8u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_A_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_A_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_A_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_A_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_A_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_A_STAT_EN_OFF (9u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_B_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_B_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_B_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_B_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_B_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_B_STAT_EN_OFF (10u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_C_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_C_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_C_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_C_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.INT_C_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_INT_C_STAT_EN_OFF (11u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.RE_TUNE_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.RE_TUNE_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.RE_TUNE_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_OFF (12u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.FX_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_FX_EVENT_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.FX_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_FX_EVENT_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.FX_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_FX_EVENT_STAT_EN_OFF (13u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CQE_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CQE_EVENT_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CQE_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CQE_EVENT_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_STAT_EN_Bits.CQE_EVENT_STAT_EN */
#define IFX_SDMMC_NORMAL_INT_STAT_EN_CQE_EVENT_STAT_EN_OFF (14u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_TOUT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_TOUT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_TOUT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_CRC_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_CRC_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_CRC_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_OFF (1u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_END_BIT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_END_BIT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_END_BIT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_IDX_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_IDX_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CMD_IDX_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_OFF (3u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_TOUT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_TOUT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_TOUT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_OFF (4u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_CRC_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_CRC_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_CRC_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_OFF (5u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_END_BIT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_END_BIT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.DATA_END_BIT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_OFF (6u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CUR_LMT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CUR_LMT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.CUR_LMT_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_OFF (7u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.AUTO_CMD_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.AUTO_CMD_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.AUTO_CMD_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_OFF (8u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.ADMA_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_ADMA_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.ADMA_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_ADMA_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.ADMA_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_ADMA_ERR_STAT_EN_OFF (9u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.TUNING_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_TUNING_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.TUNING_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_TUNING_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.TUNING_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_TUNING_ERR_STAT_EN_OFF (10u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.RESP_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_RESP_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.RESP_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_RESP_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.RESP_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_RESP_ERR_STAT_EN_OFF (11u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.BOOT_ACK_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.BOOT_ACK_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_STAT_EN_Bits.BOOT_ACK_ERR_STAT_EN */
#define IFX_SDMMC_ERROR_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_OFF (12u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CMD_COMPLETE_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CMD_COMPLETE_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CMD_COMPLETE_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.XFER_COMPLETE_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.XFER_COMPLETE_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.XFER_COMPLETE_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_OFF (1u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BGAP_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BGAP_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BGAP_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.DMA_INTERRUPT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.DMA_INTERRUPT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.DMA_INTERRUPT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_OFF (3u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BUF_WR_READY_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BUF_WR_READY_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BUF_WR_READY_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_OFF (4u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BUF_RD_READY_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BUF_RD_READY_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.BUF_RD_READY_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_OFF (5u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_INSERTION_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_INSERTION_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_INSERTION_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_OFF (6u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_REMOVAL_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_REMOVAL_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_REMOVAL_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_OFF (7u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_INTERRUPT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_INTERRUPT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CARD_INTERRUPT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_OFF (8u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_A_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_A_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_A_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_A_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_A_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_A_SIGNAL_EN_OFF (9u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_B_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_B_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_B_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_B_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_B_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_B_SIGNAL_EN_OFF (10u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_C_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_C_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_C_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_C_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.INT_C_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_INT_C_SIGNAL_EN_OFF (11u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.RE_TUNE_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.RE_TUNE_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.RE_TUNE_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_OFF (12u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.FX_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.FX_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.FX_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_OFF (13u)

/** \brief Length for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CQE_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CQE_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_NORMAL_INT_SIGNAL_EN_Bits.CQE_EVENT_SIGNAL_EN */
#define IFX_SDMMC_NORMAL_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_OFF (14u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_TOUT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_TOUT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_TOUT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_CRC_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_CRC_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_CRC_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_OFF (1u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_END_BIT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_END_BIT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_END_BIT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_IDX_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_IDX_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CMD_IDX_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_OFF (3u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_TOUT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_TOUT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_TOUT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_OFF (4u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_CRC_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_CRC_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_CRC_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_OFF (5u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_END_BIT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_END_BIT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.DATA_END_BIT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_OFF (6u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CUR_LMT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CUR_LMT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.CUR_LMT_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_OFF (7u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.AUTO_CMD_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.AUTO_CMD_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.AUTO_CMD_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_OFF (8u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.ADMA_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.ADMA_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.ADMA_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_OFF (9u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.TUNING_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.TUNING_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.TUNING_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_OFF (10u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.RESP_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.RESP_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.RESP_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_OFF (11u)

/** \brief Length for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.BOOT_ACK_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.BOOT_ACK_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ERROR_INT_SIGNAL_EN_Bits.BOOT_ACK_ERR_SIGNAL_EN */
#define IFX_SDMMC_ERROR_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_OFF (12u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD12_NOT_EXEC */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD12_NOT_EXEC_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD12_NOT_EXEC */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD12_NOT_EXEC_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD12_NOT_EXEC */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD12_NOT_EXEC_OFF (0u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_TOUT_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_TOUT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_TOUT_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_TOUT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_TOUT_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_TOUT_ERR_OFF (1u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_CRC_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_CRC_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_CRC_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_CRC_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_CRC_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_CRC_ERR_OFF (2u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_EBIT_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_EBIT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_EBIT_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_EBIT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_EBIT_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_EBIT_ERR_OFF (3u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_IDX_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_IDX_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_IDX_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_IDX_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_IDX_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_IDX_ERR_OFF (4u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_RESP_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_RESP_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_RESP_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_RESP_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.AUTO_CMD_RESP_ERR */
#define IFX_SDMMC_AUTO_CMD_STAT_AUTO_CMD_RESP_ERR_OFF (5u)

/** \brief Length for Ifx_SDMMC_AUTO_CMD_STAT_Bits.CMD_NOT_ISSUED_AUTO_CMD12 */
#define IFX_SDMMC_AUTO_CMD_STAT_CMD_NOT_ISSUED_AUTO_CMD12_LEN (1u)

/** \brief Mask for Ifx_SDMMC_AUTO_CMD_STAT_Bits.CMD_NOT_ISSUED_AUTO_CMD12 */
#define IFX_SDMMC_AUTO_CMD_STAT_CMD_NOT_ISSUED_AUTO_CMD12_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_AUTO_CMD_STAT_Bits.CMD_NOT_ISSUED_AUTO_CMD12 */
#define IFX_SDMMC_AUTO_CMD_STAT_CMD_NOT_ISSUED_AUTO_CMD12_OFF (7u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.UHS_MODE_SEL */
#define IFX_SDMMC_HOST_CTRL2_UHS_MODE_SEL_LEN (3u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.UHS_MODE_SEL */
#define IFX_SDMMC_HOST_CTRL2_UHS_MODE_SEL_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.UHS_MODE_SEL */
#define IFX_SDMMC_HOST_CTRL2_UHS_MODE_SEL_OFF (0u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.SIGNALING_EN */
#define IFX_SDMMC_HOST_CTRL2_SIGNALING_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.SIGNALING_EN */
#define IFX_SDMMC_HOST_CTRL2_SIGNALING_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.SIGNALING_EN */
#define IFX_SDMMC_HOST_CTRL2_SIGNALING_EN_OFF (3u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.DRV_STRENGTH_SEL */
#define IFX_SDMMC_HOST_CTRL2_DRV_STRENGTH_SEL_LEN (2u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.DRV_STRENGTH_SEL */
#define IFX_SDMMC_HOST_CTRL2_DRV_STRENGTH_SEL_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.DRV_STRENGTH_SEL */
#define IFX_SDMMC_HOST_CTRL2_DRV_STRENGTH_SEL_OFF (4u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.EXEC_TUNING */
#define IFX_SDMMC_HOST_CTRL2_EXEC_TUNING_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.EXEC_TUNING */
#define IFX_SDMMC_HOST_CTRL2_EXEC_TUNING_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.EXEC_TUNING */
#define IFX_SDMMC_HOST_CTRL2_EXEC_TUNING_OFF (6u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.SAMPLE_CLK_SEL */
#define IFX_SDMMC_HOST_CTRL2_SAMPLE_CLK_SEL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.SAMPLE_CLK_SEL */
#define IFX_SDMMC_HOST_CTRL2_SAMPLE_CLK_SEL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.SAMPLE_CLK_SEL */
#define IFX_SDMMC_HOST_CTRL2_SAMPLE_CLK_SEL_OFF (7u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.UHS2_IF_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_UHS2_IF_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.UHS2_IF_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_UHS2_IF_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.UHS2_IF_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_UHS2_IF_ENABLE_OFF (8u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.ADMA2_LEN_MODE */
#define IFX_SDMMC_HOST_CTRL2_ADMA2_LEN_MODE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.ADMA2_LEN_MODE */
#define IFX_SDMMC_HOST_CTRL2_ADMA2_LEN_MODE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.ADMA2_LEN_MODE */
#define IFX_SDMMC_HOST_CTRL2_ADMA2_LEN_MODE_OFF (10u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.CMD23_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_CMD23_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.CMD23_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_CMD23_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.CMD23_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_CMD23_ENABLE_OFF (11u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.HOST_VER4_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_HOST_VER4_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.HOST_VER4_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_HOST_VER4_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.HOST_VER4_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_HOST_VER4_ENABLE_OFF (12u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.ADDRESSING */
#define IFX_SDMMC_HOST_CTRL2_ADDRESSING_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.ADDRESSING */
#define IFX_SDMMC_HOST_CTRL2_ADDRESSING_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.ADDRESSING */
#define IFX_SDMMC_HOST_CTRL2_ADDRESSING_OFF (13u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.ASYNC_INT_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_ASYNC_INT_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.ASYNC_INT_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_ASYNC_INT_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.ASYNC_INT_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_ASYNC_INT_ENABLE_OFF (14u)

/** \brief Length for Ifx_SDMMC_HOST_CTRL2_Bits.PRESET_VAL_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_PRESET_VAL_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_HOST_CTRL2_Bits.PRESET_VAL_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_PRESET_VAL_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_HOST_CTRL2_Bits.PRESET_VAL_ENABLE */
#define IFX_SDMMC_HOST_CTRL2_PRESET_VAL_ENABLE_OFF (15u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.TOUT_CLK_FREQ */
#define IFX_SDMMC_CAPABILITIES1_TOUT_CLK_FREQ_LEN (6u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.TOUT_CLK_FREQ */
#define IFX_SDMMC_CAPABILITIES1_TOUT_CLK_FREQ_MSK (0x3fu)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.TOUT_CLK_FREQ */
#define IFX_SDMMC_CAPABILITIES1_TOUT_CLK_FREQ_OFF (0u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.TOUT_CLK_UNIT */
#define IFX_SDMMC_CAPABILITIES1_TOUT_CLK_UNIT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.TOUT_CLK_UNIT */
#define IFX_SDMMC_CAPABILITIES1_TOUT_CLK_UNIT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.TOUT_CLK_UNIT */
#define IFX_SDMMC_CAPABILITIES1_TOUT_CLK_UNIT_OFF (7u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.BASE_CLK_FREQ */
#define IFX_SDMMC_CAPABILITIES1_BASE_CLK_FREQ_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.BASE_CLK_FREQ */
#define IFX_SDMMC_CAPABILITIES1_BASE_CLK_FREQ_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.BASE_CLK_FREQ */
#define IFX_SDMMC_CAPABILITIES1_BASE_CLK_FREQ_OFF (8u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.MAX_BLK_LEN */
#define IFX_SDMMC_CAPABILITIES1_MAX_BLK_LEN_LEN (2u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.MAX_BLK_LEN */
#define IFX_SDMMC_CAPABILITIES1_MAX_BLK_LEN_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.MAX_BLK_LEN */
#define IFX_SDMMC_CAPABILITIES1_MAX_BLK_LEN_OFF (16u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.Embedded_8_BIT */
#define IFX_SDMMC_CAPABILITIES1_EMBEDDED_8_BIT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.Embedded_8_BIT */
#define IFX_SDMMC_CAPABILITIES1_EMBEDDED_8_BIT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.Embedded_8_BIT */
#define IFX_SDMMC_CAPABILITIES1_EMBEDDED_8_BIT_OFF (18u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.ADMA2_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_ADMA2_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.ADMA2_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_ADMA2_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.ADMA2_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_ADMA2_SUPPORT_OFF (19u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.HIGH_SPEED_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_HIGH_SPEED_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.HIGH_SPEED_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.HIGH_SPEED_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_HIGH_SPEED_SUPPORT_OFF (21u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.SDMA_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_SDMA_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.SDMA_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_SDMA_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.SDMA_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_SDMA_SUPPORT_OFF (22u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.SUS_RES_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_SUS_RES_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.SUS_RES_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_SUS_RES_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.SUS_RES_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_SUS_RES_SUPPORT_OFF (23u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_33 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_33_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_33 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_33_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_33 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_33_OFF (24u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_30 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_30_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_30 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_30_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_30 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_30_OFF (25u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_18 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_18_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_18 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_18_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.VOLT_18 */
#define IFX_SDMMC_CAPABILITIES1_VOLT_18_OFF (26u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.SYS_ADDR_64_V4 */
#define IFX_SDMMC_CAPABILITIES1_SYS_ADDR_64_V4_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.SYS_ADDR_64_V4 */
#define IFX_SDMMC_CAPABILITIES1_SYS_ADDR_64_V4_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.SYS_ADDR_64_V4 */
#define IFX_SDMMC_CAPABILITIES1_SYS_ADDR_64_V4_OFF (27u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.SYS_ADDR_64_V3 */
#define IFX_SDMMC_CAPABILITIES1_SYS_ADDR_64_V3_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.SYS_ADDR_64_V3 */
#define IFX_SDMMC_CAPABILITIES1_SYS_ADDR_64_V3_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.SYS_ADDR_64_V3 */
#define IFX_SDMMC_CAPABILITIES1_SYS_ADDR_64_V3_OFF (28u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.ASYNC_INT_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_ASYNC_INT_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.ASYNC_INT_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_ASYNC_INT_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.ASYNC_INT_SUPPORT */
#define IFX_SDMMC_CAPABILITIES1_ASYNC_INT_SUPPORT_OFF (29u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES1_Bits.SLOT_TYPE */
#define IFX_SDMMC_CAPABILITIES1_SLOT_TYPE_LEN (2u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES1_Bits.SLOT_TYPE */
#define IFX_SDMMC_CAPABILITIES1_SLOT_TYPE_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES1_Bits.SLOT_TYPE */
#define IFX_SDMMC_CAPABILITIES1_SLOT_TYPE_OFF (30u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.SDR50_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_SDR50_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.SDR50_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_SDR50_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.SDR50_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_SDR50_SUPPORT_OFF (0u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.SDR104_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_SDR104_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.SDR104_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_SDR104_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.SDR104_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_SDR104_SUPPORT_OFF (1u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.DDR50_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_DDR50_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.DDR50_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_DDR50_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.DDR50_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_DDR50_SUPPORT_OFF (2u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.UHS2_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_UHS2_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.UHS2_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_UHS2_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.UHS2_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_UHS2_SUPPORT_OFF (3u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPEA */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPEA_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPEA */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPEA_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPEA */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPEA_OFF (4u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPEC */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPEC_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPEC */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPEC_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPEC */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPEC_OFF (5u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPED */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPED_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPED */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPED_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.DRV_TYPED */
#define IFX_SDMMC_CAPABILITIES2_DRV_TYPED_OFF (6u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.RETUNE_CNT */
#define IFX_SDMMC_CAPABILITIES2_RETUNE_CNT_LEN (4u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.RETUNE_CNT */
#define IFX_SDMMC_CAPABILITIES2_RETUNE_CNT_MSK (0xfu)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.RETUNE_CNT */
#define IFX_SDMMC_CAPABILITIES2_RETUNE_CNT_OFF (8u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.USE_TUNING_SDR50 */
#define IFX_SDMMC_CAPABILITIES2_USE_TUNING_SDR50_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.USE_TUNING_SDR50 */
#define IFX_SDMMC_CAPABILITIES2_USE_TUNING_SDR50_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.USE_TUNING_SDR50 */
#define IFX_SDMMC_CAPABILITIES2_USE_TUNING_SDR50_OFF (13u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.RE_TUNING_MODES */
#define IFX_SDMMC_CAPABILITIES2_RE_TUNING_MODES_LEN (2u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.RE_TUNING_MODES */
#define IFX_SDMMC_CAPABILITIES2_RE_TUNING_MODES_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.RE_TUNING_MODES */
#define IFX_SDMMC_CAPABILITIES2_RE_TUNING_MODES_OFF (14u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.CLK_MUL */
#define IFX_SDMMC_CAPABILITIES2_CLK_MUL_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.CLK_MUL */
#define IFX_SDMMC_CAPABILITIES2_CLK_MUL_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.CLK_MUL */
#define IFX_SDMMC_CAPABILITIES2_CLK_MUL_OFF (16u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.ADMA3_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_ADMA3_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.ADMA3_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_ADMA3_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.ADMA3_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_ADMA3_SUPPORT_OFF (27u)

/** \brief Length for Ifx_SDMMC_CAPABILITIES2_Bits.VDD2_18V_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_VDD2_18V_SUPPORT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CAPABILITIES2_Bits.VDD2_18V_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_VDD2_18V_SUPPORT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CAPABILITIES2_Bits.VDD2_18V_SUPPORT */
#define IFX_SDMMC_CAPABILITIES2_VDD2_18V_SUPPORT_OFF (28u)

/** \brief Length for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_33V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_33V_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_33V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_33V_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_33V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_33V_OFF (0u)

/** \brief Length for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_30V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_30V_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_30V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_30V_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_30V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_30V_OFF (8u)

/** \brief Length for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_18V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_18V_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_18V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_18V_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CURR_CAPABILITIES1_Bits.MAX_CUR_18V */
#define IFX_SDMMC_CURR_CAPABILITIES1_MAX_CUR_18V_OFF (16u)

/** \brief Length for Ifx_SDMMC_CURR_CAPABILITIES2_Bits.MAX_CUR_VDD2_18V */
#define IFX_SDMMC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_LEN (8u)

/** \brief Mask for Ifx_SDMMC_CURR_CAPABILITIES2_Bits.MAX_CUR_VDD2_18V */
#define IFX_SDMMC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_CURR_CAPABILITIES2_Bits.MAX_CUR_VDD2_18V */
#define IFX_SDMMC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_OFF (0u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD12_NOT_EXEC */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD12_NOT_EXEC_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD12_NOT_EXEC */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD12_NOT_EXEC_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD12_NOT_EXEC */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD12_NOT_EXEC_OFF (0u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_TOUT_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_TOUT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_TOUT_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_TOUT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_TOUT_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_TOUT_ERR_OFF (1u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_CRC_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_CRC_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_CRC_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_CRC_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_CRC_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_CRC_ERR_OFF (2u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_EBIT_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_EBIT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_EBIT_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_EBIT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_EBIT_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_EBIT_ERR_OFF (3u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_IDX_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_IDX_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_IDX_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_IDX_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_IDX_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_IDX_ERR_OFF (4u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_RESP_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_RESP_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_RESP_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_RESP_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_AUTO_CMD_RESP_ERR */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_AUTO_CMD_RESP_ERR_OFF (5u)

/** \brief Length for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_CMD_NOT_ISSUED_AUTO_CMD12 */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_CMD_NOT_ISSUED_AUTO_CMD12 */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_AUTO_CMD_STAT_Bits.FORCE_CMD_NOT_ISSUED_AUTO_CMD12 */
#define IFX_SDMMC_FORCE_AUTO_CMD_STAT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_OFF (7u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_TOUT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_TOUT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_TOUT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_TOUT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_TOUT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_TOUT_ERR_OFF (0u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_CRC_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_CRC_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_CRC_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_CRC_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_CRC_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_CRC_ERR_OFF (1u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_END_BIT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_END_BIT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_END_BIT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_END_BIT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_END_BIT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_END_BIT_ERR_OFF (2u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_IDX_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_IDX_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_IDX_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_IDX_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CMD_IDX_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CMD_IDX_ERR_OFF (3u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_TOUT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_TOUT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_TOUT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_TOUT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_TOUT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_TOUT_ERR_OFF (4u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_CRC_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_CRC_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_CRC_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_CRC_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_CRC_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_CRC_ERR_OFF (5u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_END_BIT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_END_BIT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_END_BIT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_END_BIT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_DATA_END_BIT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_DATA_END_BIT_ERR_OFF (6u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CUR_LMT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CUR_LMT_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CUR_LMT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CUR_LMT_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_CUR_LMT_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_CUR_LMT_ERR_OFF (7u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_AUTO_CMD_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_AUTO_CMD_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_AUTO_CMD_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_AUTO_CMD_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_AUTO_CMD_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_AUTO_CMD_ERR_OFF (8u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_ADMA_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_ADMA_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_ADMA_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_ADMA_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_ADMA_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_ADMA_ERR_OFF (9u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_TUNING_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_TUNING_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_TUNING_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_TUNING_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_TUNING_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_TUNING_ERR_OFF (10u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_RESP_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_RESP_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_RESP_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_RESP_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_RESP_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_RESP_ERR_OFF (11u)

/** \brief Length for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_BOOT_ACK_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_BOOT_ACK_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_BOOT_ACK_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_BOOT_ACK_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_FORCE_ERROR_INT_STAT_Bits.FORCE_BOOT_ACK_ERR */
#define IFX_SDMMC_FORCE_ERROR_INT_STAT_FORCE_BOOT_ACK_ERR_OFF (12u)

/** \brief Length for Ifx_SDMMC_ADMA_ERR_STAT_Bits.ADMA_ERR_STATES */
#define IFX_SDMMC_ADMA_ERR_STAT_ADMA_ERR_STATES_LEN (2u)

/** \brief Mask for Ifx_SDMMC_ADMA_ERR_STAT_Bits.ADMA_ERR_STATES */
#define IFX_SDMMC_ADMA_ERR_STAT_ADMA_ERR_STATES_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_ADMA_ERR_STAT_Bits.ADMA_ERR_STATES */
#define IFX_SDMMC_ADMA_ERR_STAT_ADMA_ERR_STATES_OFF (0u)

/** \brief Length for Ifx_SDMMC_ADMA_ERR_STAT_Bits.ADMA_LEN_ERR */
#define IFX_SDMMC_ADMA_ERR_STAT_ADMA_LEN_ERR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ADMA_ERR_STAT_Bits.ADMA_LEN_ERR */
#define IFX_SDMMC_ADMA_ERR_STAT_ADMA_LEN_ERR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ADMA_ERR_STAT_Bits.ADMA_LEN_ERR */
#define IFX_SDMMC_ADMA_ERR_STAT_ADMA_LEN_ERR_OFF (2u)

/** \brief Length for Ifx_SDMMC_ADMA_SA_LOW_Bits.ADMA_SA_LOW */
#define IFX_SDMMC_ADMA_SA_LOW_ADMA_SA_LOW_LEN (32u)

/** \brief Mask for Ifx_SDMMC_ADMA_SA_LOW_Bits.ADMA_SA_LOW */
#define IFX_SDMMC_ADMA_SA_LOW_ADMA_SA_LOW_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_ADMA_SA_LOW_Bits.ADMA_SA_LOW */
#define IFX_SDMMC_ADMA_SA_LOW_ADMA_SA_LOW_OFF (0u)

/** \brief Length for Ifx_SDMMC_PRESET_INIT_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_FREQ_SEL_VAL_LEN (10u)

/** \brief Mask for Ifx_SDMMC_PRESET_INIT_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_FREQ_SEL_VAL_MSK (0x3ffu)

/** \brief Offset for Ifx_SDMMC_PRESET_INIT_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_FREQ_SEL_VAL_OFF (0u)

/** \brief Length for Ifx_SDMMC_PRESET_INIT_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_CLK_GEN_SEL_VAL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PRESET_INIT_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_CLK_GEN_SEL_VAL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PRESET_INIT_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_CLK_GEN_SEL_VAL_OFF (10u)

/** \brief Length for Ifx_SDMMC_PRESET_INIT_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_DRV_SEL_VAL_LEN (2u)

/** \brief Mask for Ifx_SDMMC_PRESET_INIT_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_DRV_SEL_VAL_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_PRESET_INIT_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_INIT_DRV_SEL_VAL_OFF (14u)

/** \brief Length for Ifx_SDMMC_PRESET_DS_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_FREQ_SEL_VAL_LEN (10u)

/** \brief Mask for Ifx_SDMMC_PRESET_DS_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_FREQ_SEL_VAL_MSK (0x3ffu)

/** \brief Offset for Ifx_SDMMC_PRESET_DS_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_FREQ_SEL_VAL_OFF (0u)

/** \brief Length for Ifx_SDMMC_PRESET_DS_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_CLK_GEN_SEL_VAL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PRESET_DS_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_CLK_GEN_SEL_VAL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PRESET_DS_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_CLK_GEN_SEL_VAL_OFF (10u)

/** \brief Length for Ifx_SDMMC_PRESET_DS_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_DRV_SEL_VAL_LEN (2u)

/** \brief Mask for Ifx_SDMMC_PRESET_DS_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_DRV_SEL_VAL_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_PRESET_DS_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_DS_DRV_SEL_VAL_OFF (14u)

/** \brief Length for Ifx_SDMMC_PRESET_HS_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_FREQ_SEL_VAL_LEN (10u)

/** \brief Mask for Ifx_SDMMC_PRESET_HS_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_FREQ_SEL_VAL_MSK (0x3ffu)

/** \brief Offset for Ifx_SDMMC_PRESET_HS_Bits.FREQ_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_FREQ_SEL_VAL_OFF (0u)

/** \brief Length for Ifx_SDMMC_PRESET_HS_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_CLK_GEN_SEL_VAL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_PRESET_HS_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_CLK_GEN_SEL_VAL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_PRESET_HS_Bits.CLK_GEN_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_CLK_GEN_SEL_VAL_OFF (10u)

/** \brief Length for Ifx_SDMMC_PRESET_HS_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_DRV_SEL_VAL_LEN (2u)

/** \brief Mask for Ifx_SDMMC_PRESET_HS_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_DRV_SEL_VAL_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_PRESET_HS_Bits.DRV_SEL_VAL */
#define IFX_SDMMC_PRESET_HS_DRV_SEL_VAL_OFF (14u)

/** \brief Length for Ifx_SDMMC_ADMA_ID_LOW_Bits.ADMA_ID_LOW */
#define IFX_SDMMC_ADMA_ID_LOW_ADMA_ID_LOW_LEN (32u)

/** \brief Mask for Ifx_SDMMC_ADMA_ID_LOW_Bits.ADMA_ID_LOW */
#define IFX_SDMMC_ADMA_ID_LOW_ADMA_ID_LOW_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_ADMA_ID_LOW_Bits.ADMA_ID_LOW */
#define IFX_SDMMC_ADMA_ID_LOW_ADMA_ID_LOW_OFF (0u)

/** \brief Length for Ifx_SDMMC_P_VENDOR_SPECIFIC_AREA_Bits.REG_OFFSET_ADDR */
#define IFX_SDMMC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_LEN (12u)

/** \brief Mask for Ifx_SDMMC_P_VENDOR_SPECIFIC_AREA_Bits.REG_OFFSET_ADDR */
#define IFX_SDMMC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MSK (0xfffu)

/** \brief Offset for Ifx_SDMMC_P_VENDOR_SPECIFIC_AREA_Bits.REG_OFFSET_ADDR */
#define IFX_SDMMC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_OFF (0u)

/** \brief Length for Ifx_SDMMC_P_VENDOR2_SPECIFIC_AREA_Bits.REG_OFFSET_ADDR */
#define IFX_SDMMC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_LEN (12u)

/** \brief Mask for Ifx_SDMMC_P_VENDOR2_SPECIFIC_AREA_Bits.REG_OFFSET_ADDR */
#define IFX_SDMMC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MSK (0xfffu)

/** \brief Offset for Ifx_SDMMC_P_VENDOR2_SPECIFIC_AREA_Bits.REG_OFFSET_ADDR */
#define IFX_SDMMC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_OFF (0u)

/** \brief Length for Ifx_SDMMC_SLOT_INTR_STATUS_Bits.INTR_SLOT */
#define IFX_SDMMC_SLOT_INTR_STATUS_INTR_SLOT_LEN (8u)

/** \brief Mask for Ifx_SDMMC_SLOT_INTR_STATUS_Bits.INTR_SLOT */
#define IFX_SDMMC_SLOT_INTR_STATUS_INTR_SLOT_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_SLOT_INTR_STATUS_Bits.INTR_SLOT */
#define IFX_SDMMC_SLOT_INTR_STATUS_INTR_SLOT_OFF (0u)

/** \brief Length for Ifx_SDMMC_HOST_CNTRL_VERS_Bits.SPEC_VERSION_NUM */
#define IFX_SDMMC_HOST_CNTRL_VERS_SPEC_VERSION_NUM_LEN (8u)

/** \brief Mask for Ifx_SDMMC_HOST_CNTRL_VERS_Bits.SPEC_VERSION_NUM */
#define IFX_SDMMC_HOST_CNTRL_VERS_SPEC_VERSION_NUM_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_HOST_CNTRL_VERS_Bits.SPEC_VERSION_NUM */
#define IFX_SDMMC_HOST_CNTRL_VERS_SPEC_VERSION_NUM_OFF (0u)

/** \brief Length for Ifx_SDMMC_HOST_CNTRL_VERS_Bits.VENDOR_VERSION_NUM */
#define IFX_SDMMC_HOST_CNTRL_VERS_VENDOR_VERSION_NUM_LEN (8u)

/** \brief Mask for Ifx_SDMMC_HOST_CNTRL_VERS_Bits.VENDOR_VERSION_NUM */
#define IFX_SDMMC_HOST_CNTRL_VERS_VENDOR_VERSION_NUM_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_HOST_CNTRL_VERS_Bits.VENDOR_VERSION_NUM */
#define IFX_SDMMC_HOST_CNTRL_VERS_VENDOR_VERSION_NUM_OFF (8u)

/** \brief Length for Ifx_SDMMC_MSHC_VER_ID_Bits.MSHC_VER_ID */
#define IFX_SDMMC_MSHC_VER_ID_MSHC_VER_ID_LEN (32u)

/** \brief Mask for Ifx_SDMMC_MSHC_VER_ID_Bits.MSHC_VER_ID */
#define IFX_SDMMC_MSHC_VER_ID_MSHC_VER_ID_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_MSHC_VER_ID_Bits.MSHC_VER_ID */
#define IFX_SDMMC_MSHC_VER_ID_MSHC_VER_ID_OFF (0u)

/** \brief Length for Ifx_SDMMC_MSHC_VER_TYPE_Bits.MSHC_VER_TYPE */
#define IFX_SDMMC_MSHC_VER_TYPE_MSHC_VER_TYPE_LEN (32u)

/** \brief Mask for Ifx_SDMMC_MSHC_VER_TYPE_Bits.MSHC_VER_TYPE */
#define IFX_SDMMC_MSHC_VER_TYPE_MSHC_VER_TYPE_MSK (0xffffffffu)

/** \brief Offset for Ifx_SDMMC_MSHC_VER_TYPE_Bits.MSHC_VER_TYPE */
#define IFX_SDMMC_MSHC_VER_TYPE_MSHC_VER_TYPE_OFF (0u)

/** \brief Length for Ifx_SDMMC_MBIU_CTRL_Bits.UNDEFL_INCR_EN */
#define IFX_SDMMC_MBIU_CTRL_UNDEFL_INCR_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_MBIU_CTRL_Bits.UNDEFL_INCR_EN */
#define IFX_SDMMC_MBIU_CTRL_UNDEFL_INCR_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_MBIU_CTRL_Bits.UNDEFL_INCR_EN */
#define IFX_SDMMC_MBIU_CTRL_UNDEFL_INCR_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR4_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR4_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR4_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR4_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR4_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR4_EN_OFF (1u)

/** \brief Length for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR8_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR8_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR8_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR8_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR8_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR8_EN_OFF (2u)

/** \brief Length for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR16_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR16_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR16_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR16_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_MBIU_CTRL_Bits.BURST_INCR16_EN */
#define IFX_SDMMC_MBIU_CTRL_BURST_INCR16_EN_OFF (3u)

/** \brief Length for Ifx_SDMMC_EMMC_CTRL_Bits.CARD_IS_EMMC */
#define IFX_SDMMC_EMMC_CTRL_CARD_IS_EMMC_LEN (1u)

/** \brief Mask for Ifx_SDMMC_EMMC_CTRL_Bits.CARD_IS_EMMC */
#define IFX_SDMMC_EMMC_CTRL_CARD_IS_EMMC_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_EMMC_CTRL_Bits.CARD_IS_EMMC */
#define IFX_SDMMC_EMMC_CTRL_CARD_IS_EMMC_OFF (0u)

/** \brief Length for Ifx_SDMMC_EMMC_CTRL_Bits.DISABLE_DATA_CRC_CHK */
#define IFX_SDMMC_EMMC_CTRL_DISABLE_DATA_CRC_CHK_LEN (1u)

/** \brief Mask for Ifx_SDMMC_EMMC_CTRL_Bits.DISABLE_DATA_CRC_CHK */
#define IFX_SDMMC_EMMC_CTRL_DISABLE_DATA_CRC_CHK_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_EMMC_CTRL_Bits.DISABLE_DATA_CRC_CHK */
#define IFX_SDMMC_EMMC_CTRL_DISABLE_DATA_CRC_CHK_OFF (1u)

/** \brief Length for Ifx_SDMMC_EMMC_CTRL_Bits.ENH_STROBE_ENABLE */
#define IFX_SDMMC_EMMC_CTRL_ENH_STROBE_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_EMMC_CTRL_Bits.ENH_STROBE_ENABLE */
#define IFX_SDMMC_EMMC_CTRL_ENH_STROBE_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_EMMC_CTRL_Bits.ENH_STROBE_ENABLE */
#define IFX_SDMMC_EMMC_CTRL_ENH_STROBE_ENABLE_OFF (8u)

/** \brief Length for Ifx_SDMMC_EMMC_CTRL_Bits.CQE_ALGO_SEL */
#define IFX_SDMMC_EMMC_CTRL_CQE_ALGO_SEL_LEN (1u)

/** \brief Mask for Ifx_SDMMC_EMMC_CTRL_Bits.CQE_ALGO_SEL */
#define IFX_SDMMC_EMMC_CTRL_CQE_ALGO_SEL_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_EMMC_CTRL_Bits.CQE_ALGO_SEL */
#define IFX_SDMMC_EMMC_CTRL_CQE_ALGO_SEL_OFF (9u)

/** \brief Length for Ifx_SDMMC_BOOT_CTRL_Bits.MAN_BOOT_EN */
#define IFX_SDMMC_BOOT_CTRL_MAN_BOOT_EN_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BOOT_CTRL_Bits.MAN_BOOT_EN */
#define IFX_SDMMC_BOOT_CTRL_MAN_BOOT_EN_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BOOT_CTRL_Bits.MAN_BOOT_EN */
#define IFX_SDMMC_BOOT_CTRL_MAN_BOOT_EN_OFF (0u)

/** \brief Length for Ifx_SDMMC_BOOT_CTRL_Bits.VALIDATE_BOOT */
#define IFX_SDMMC_BOOT_CTRL_VALIDATE_BOOT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BOOT_CTRL_Bits.VALIDATE_BOOT */
#define IFX_SDMMC_BOOT_CTRL_VALIDATE_BOOT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BOOT_CTRL_Bits.VALIDATE_BOOT */
#define IFX_SDMMC_BOOT_CTRL_VALIDATE_BOOT_OFF (7u)

/** \brief Length for Ifx_SDMMC_BOOT_CTRL_Bits.BOOT_ACK_ENABLE */
#define IFX_SDMMC_BOOT_CTRL_BOOT_ACK_ENABLE_LEN (1u)

/** \brief Mask for Ifx_SDMMC_BOOT_CTRL_Bits.BOOT_ACK_ENABLE */
#define IFX_SDMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_BOOT_CTRL_Bits.BOOT_ACK_ENABLE */
#define IFX_SDMMC_BOOT_CTRL_BOOT_ACK_ENABLE_OFF (8u)

/** \brief Length for Ifx_SDMMC_BOOT_CTRL_Bits.BOOT_TOUT_CNT */
#define IFX_SDMMC_BOOT_CTRL_BOOT_TOUT_CNT_LEN (4u)

/** \brief Mask for Ifx_SDMMC_BOOT_CTRL_Bits.BOOT_TOUT_CNT */
#define IFX_SDMMC_BOOT_CTRL_BOOT_TOUT_CNT_MSK (0xfu)

/** \brief Offset for Ifx_SDMMC_BOOT_CTRL_Bits.BOOT_TOUT_CNT */
#define IFX_SDMMC_BOOT_CTRL_BOOT_TOUT_CNT_OFF (12u)

/** \brief Length for Ifx_SDMMC_EMBEDDED_CTRL_Bits.NUM_CLK_PIN */
#define IFX_SDMMC_EMBEDDED_CTRL_NUM_CLK_PIN_LEN (3u)

/** \brief Mask for Ifx_SDMMC_EMBEDDED_CTRL_Bits.NUM_CLK_PIN */
#define IFX_SDMMC_EMBEDDED_CTRL_NUM_CLK_PIN_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_EMBEDDED_CTRL_Bits.NUM_CLK_PIN */
#define IFX_SDMMC_EMBEDDED_CTRL_NUM_CLK_PIN_OFF (0u)

/** \brief Length for Ifx_SDMMC_EMBEDDED_CTRL_Bits.NUM_INT_PIN */
#define IFX_SDMMC_EMBEDDED_CTRL_NUM_INT_PIN_LEN (2u)

/** \brief Mask for Ifx_SDMMC_EMBEDDED_CTRL_Bits.NUM_INT_PIN */
#define IFX_SDMMC_EMBEDDED_CTRL_NUM_INT_PIN_MSK (0x3u)

/** \brief Offset for Ifx_SDMMC_EMBEDDED_CTRL_Bits.NUM_INT_PIN */
#define IFX_SDMMC_EMBEDDED_CTRL_NUM_INT_PIN_OFF (4u)

/** \brief Length for Ifx_SDMMC_EMBEDDED_CTRL_Bits.BUS_WIDTH_PRESET */
#define IFX_SDMMC_EMBEDDED_CTRL_BUS_WIDTH_PRESET_LEN (7u)

/** \brief Mask for Ifx_SDMMC_EMBEDDED_CTRL_Bits.BUS_WIDTH_PRESET */
#define IFX_SDMMC_EMBEDDED_CTRL_BUS_WIDTH_PRESET_MSK (0x7fu)

/** \brief Offset for Ifx_SDMMC_EMBEDDED_CTRL_Bits.BUS_WIDTH_PRESET */
#define IFX_SDMMC_EMBEDDED_CTRL_BUS_WIDTH_PRESET_OFF (8u)

/** \brief Length for Ifx_SDMMC_EMBEDDED_CTRL_Bits.CLK_PIN_SEL */
#define IFX_SDMMC_EMBEDDED_CTRL_CLK_PIN_SEL_LEN (3u)

/** \brief Mask for Ifx_SDMMC_EMBEDDED_CTRL_Bits.CLK_PIN_SEL */
#define IFX_SDMMC_EMBEDDED_CTRL_CLK_PIN_SEL_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_EMBEDDED_CTRL_Bits.CLK_PIN_SEL */
#define IFX_SDMMC_EMBEDDED_CTRL_CLK_PIN_SEL_OFF (16u)

/** \brief Length for Ifx_SDMMC_EMBEDDED_CTRL_Bits.INT_PIN_SEL */
#define IFX_SDMMC_EMBEDDED_CTRL_INT_PIN_SEL_LEN (3u)

/** \brief Mask for Ifx_SDMMC_EMBEDDED_CTRL_Bits.INT_PIN_SEL */
#define IFX_SDMMC_EMBEDDED_CTRL_INT_PIN_SEL_MSK (0x7u)

/** \brief Offset for Ifx_SDMMC_EMBEDDED_CTRL_Bits.INT_PIN_SEL */
#define IFX_SDMMC_EMBEDDED_CTRL_INT_PIN_SEL_OFF (20u)

/** \brief Length for Ifx_SDMMC_EMBEDDED_CTRL_Bits.BACK_END_PWR_CTRL */
#define IFX_SDMMC_EMBEDDED_CTRL_BACK_END_PWR_CTRL_LEN (7u)

/** \brief Mask for Ifx_SDMMC_EMBEDDED_CTRL_Bits.BACK_END_PWR_CTRL */
#define IFX_SDMMC_EMBEDDED_CTRL_BACK_END_PWR_CTRL_MSK (0x7fu)

/** \brief Offset for Ifx_SDMMC_EMBEDDED_CTRL_Bits.BACK_END_PWR_CTRL */
#define IFX_SDMMC_EMBEDDED_CTRL_BACK_END_PWR_CTRL_OFF (24u)

/** \brief Length for Ifx_SDMMC_CLC_Bits.DISR */
#define IFX_SDMMC_CLC_DISR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLC_Bits.DISR */
#define IFX_SDMMC_CLC_DISR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLC_Bits.DISR */
#define IFX_SDMMC_CLC_DISR_OFF (0u)

/** \brief Length for Ifx_SDMMC_CLC_Bits.DISS */
#define IFX_SDMMC_CLC_DISS_LEN (1u)

/** \brief Mask for Ifx_SDMMC_CLC_Bits.DISS */
#define IFX_SDMMC_CLC_DISS_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_CLC_Bits.DISS */
#define IFX_SDMMC_CLC_DISS_OFF (1u)

/** \brief Length for Ifx_SDMMC_ID_Bits.MODREV */
#define IFX_SDMMC_ID_MODREV_LEN (8u)

/** \brief Mask for Ifx_SDMMC_ID_Bits.MODREV */
#define IFX_SDMMC_ID_MODREV_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_ID_Bits.MODREV */
#define IFX_SDMMC_ID_MODREV_OFF (0u)

/** \brief Length for Ifx_SDMMC_ID_Bits.MODTYPE */
#define IFX_SDMMC_ID_MODTYPE_LEN (8u)

/** \brief Mask for Ifx_SDMMC_ID_Bits.MODTYPE */
#define IFX_SDMMC_ID_MODTYPE_MSK (0xffu)

/** \brief Offset for Ifx_SDMMC_ID_Bits.MODTYPE */
#define IFX_SDMMC_ID_MODTYPE_OFF (8u)

/** \brief Length for Ifx_SDMMC_ID_Bits.MODNUM */
#define IFX_SDMMC_ID_MODNUM_LEN (16u)

/** \brief Mask for Ifx_SDMMC_ID_Bits.MODNUM */
#define IFX_SDMMC_ID_MODNUM_MSK (0xffffu)

/** \brief Offset for Ifx_SDMMC_ID_Bits.MODNUM */
#define IFX_SDMMC_ID_MODNUM_OFF (16u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN0 */
#define IFX_SDMMC_ACCEN0_EN0_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN0 */
#define IFX_SDMMC_ACCEN0_EN0_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN0 */
#define IFX_SDMMC_ACCEN0_EN0_OFF (0u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN1 */
#define IFX_SDMMC_ACCEN0_EN1_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN1 */
#define IFX_SDMMC_ACCEN0_EN1_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN1 */
#define IFX_SDMMC_ACCEN0_EN1_OFF (1u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN2 */
#define IFX_SDMMC_ACCEN0_EN2_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN2 */
#define IFX_SDMMC_ACCEN0_EN2_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN2 */
#define IFX_SDMMC_ACCEN0_EN2_OFF (2u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN3 */
#define IFX_SDMMC_ACCEN0_EN3_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN3 */
#define IFX_SDMMC_ACCEN0_EN3_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN3 */
#define IFX_SDMMC_ACCEN0_EN3_OFF (3u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN4 */
#define IFX_SDMMC_ACCEN0_EN4_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN4 */
#define IFX_SDMMC_ACCEN0_EN4_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN4 */
#define IFX_SDMMC_ACCEN0_EN4_OFF (4u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN5 */
#define IFX_SDMMC_ACCEN0_EN5_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN5 */
#define IFX_SDMMC_ACCEN0_EN5_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN5 */
#define IFX_SDMMC_ACCEN0_EN5_OFF (5u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN6 */
#define IFX_SDMMC_ACCEN0_EN6_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN6 */
#define IFX_SDMMC_ACCEN0_EN6_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN6 */
#define IFX_SDMMC_ACCEN0_EN6_OFF (6u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN7 */
#define IFX_SDMMC_ACCEN0_EN7_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN7 */
#define IFX_SDMMC_ACCEN0_EN7_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN7 */
#define IFX_SDMMC_ACCEN0_EN7_OFF (7u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN8 */
#define IFX_SDMMC_ACCEN0_EN8_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN8 */
#define IFX_SDMMC_ACCEN0_EN8_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN8 */
#define IFX_SDMMC_ACCEN0_EN8_OFF (8u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN9 */
#define IFX_SDMMC_ACCEN0_EN9_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN9 */
#define IFX_SDMMC_ACCEN0_EN9_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN9 */
#define IFX_SDMMC_ACCEN0_EN9_OFF (9u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN10 */
#define IFX_SDMMC_ACCEN0_EN10_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN10 */
#define IFX_SDMMC_ACCEN0_EN10_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN10 */
#define IFX_SDMMC_ACCEN0_EN10_OFF (10u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN11 */
#define IFX_SDMMC_ACCEN0_EN11_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN11 */
#define IFX_SDMMC_ACCEN0_EN11_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN11 */
#define IFX_SDMMC_ACCEN0_EN11_OFF (11u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN12 */
#define IFX_SDMMC_ACCEN0_EN12_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN12 */
#define IFX_SDMMC_ACCEN0_EN12_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN12 */
#define IFX_SDMMC_ACCEN0_EN12_OFF (12u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN13 */
#define IFX_SDMMC_ACCEN0_EN13_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN13 */
#define IFX_SDMMC_ACCEN0_EN13_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN13 */
#define IFX_SDMMC_ACCEN0_EN13_OFF (13u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN14 */
#define IFX_SDMMC_ACCEN0_EN14_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN14 */
#define IFX_SDMMC_ACCEN0_EN14_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN14 */
#define IFX_SDMMC_ACCEN0_EN14_OFF (14u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN15 */
#define IFX_SDMMC_ACCEN0_EN15_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN15 */
#define IFX_SDMMC_ACCEN0_EN15_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN15 */
#define IFX_SDMMC_ACCEN0_EN15_OFF (15u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN16 */
#define IFX_SDMMC_ACCEN0_EN16_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN16 */
#define IFX_SDMMC_ACCEN0_EN16_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN16 */
#define IFX_SDMMC_ACCEN0_EN16_OFF (16u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN17 */
#define IFX_SDMMC_ACCEN0_EN17_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN17 */
#define IFX_SDMMC_ACCEN0_EN17_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN17 */
#define IFX_SDMMC_ACCEN0_EN17_OFF (17u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN18 */
#define IFX_SDMMC_ACCEN0_EN18_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN18 */
#define IFX_SDMMC_ACCEN0_EN18_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN18 */
#define IFX_SDMMC_ACCEN0_EN18_OFF (18u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN19 */
#define IFX_SDMMC_ACCEN0_EN19_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN19 */
#define IFX_SDMMC_ACCEN0_EN19_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN19 */
#define IFX_SDMMC_ACCEN0_EN19_OFF (19u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN20 */
#define IFX_SDMMC_ACCEN0_EN20_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN20 */
#define IFX_SDMMC_ACCEN0_EN20_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN20 */
#define IFX_SDMMC_ACCEN0_EN20_OFF (20u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN21 */
#define IFX_SDMMC_ACCEN0_EN21_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN21 */
#define IFX_SDMMC_ACCEN0_EN21_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN21 */
#define IFX_SDMMC_ACCEN0_EN21_OFF (21u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN22 */
#define IFX_SDMMC_ACCEN0_EN22_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN22 */
#define IFX_SDMMC_ACCEN0_EN22_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN22 */
#define IFX_SDMMC_ACCEN0_EN22_OFF (22u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN23 */
#define IFX_SDMMC_ACCEN0_EN23_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN23 */
#define IFX_SDMMC_ACCEN0_EN23_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN23 */
#define IFX_SDMMC_ACCEN0_EN23_OFF (23u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN24 */
#define IFX_SDMMC_ACCEN0_EN24_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN24 */
#define IFX_SDMMC_ACCEN0_EN24_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN24 */
#define IFX_SDMMC_ACCEN0_EN24_OFF (24u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN25 */
#define IFX_SDMMC_ACCEN0_EN25_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN25 */
#define IFX_SDMMC_ACCEN0_EN25_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN25 */
#define IFX_SDMMC_ACCEN0_EN25_OFF (25u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN26 */
#define IFX_SDMMC_ACCEN0_EN26_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN26 */
#define IFX_SDMMC_ACCEN0_EN26_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN26 */
#define IFX_SDMMC_ACCEN0_EN26_OFF (26u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN27 */
#define IFX_SDMMC_ACCEN0_EN27_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN27 */
#define IFX_SDMMC_ACCEN0_EN27_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN27 */
#define IFX_SDMMC_ACCEN0_EN27_OFF (27u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN28 */
#define IFX_SDMMC_ACCEN0_EN28_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN28 */
#define IFX_SDMMC_ACCEN0_EN28_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN28 */
#define IFX_SDMMC_ACCEN0_EN28_OFF (28u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN29 */
#define IFX_SDMMC_ACCEN0_EN29_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN29 */
#define IFX_SDMMC_ACCEN0_EN29_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN29 */
#define IFX_SDMMC_ACCEN0_EN29_OFF (29u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN30 */
#define IFX_SDMMC_ACCEN0_EN30_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN30 */
#define IFX_SDMMC_ACCEN0_EN30_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN30 */
#define IFX_SDMMC_ACCEN0_EN30_OFF (30u)

/** \brief Length for Ifx_SDMMC_ACCEN0_Bits.EN31 */
#define IFX_SDMMC_ACCEN0_EN31_LEN (1u)

/** \brief Mask for Ifx_SDMMC_ACCEN0_Bits.EN31 */
#define IFX_SDMMC_ACCEN0_EN31_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_ACCEN0_Bits.EN31 */
#define IFX_SDMMC_ACCEN0_EN31_OFF (31u)

/** \brief Length for Ifx_SDMMC_KRST0_Bits.RST */
#define IFX_SDMMC_KRST0_RST_LEN (1u)

/** \brief Mask for Ifx_SDMMC_KRST0_Bits.RST */
#define IFX_SDMMC_KRST0_RST_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_KRST0_Bits.RST */
#define IFX_SDMMC_KRST0_RST_OFF (0u)

/** \brief Length for Ifx_SDMMC_KRST0_Bits.RSTSTAT */
#define IFX_SDMMC_KRST0_RSTSTAT_LEN (1u)

/** \brief Mask for Ifx_SDMMC_KRST0_Bits.RSTSTAT */
#define IFX_SDMMC_KRST0_RSTSTAT_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_KRST0_Bits.RSTSTAT */
#define IFX_SDMMC_KRST0_RSTSTAT_OFF (1u)

/** \brief Length for Ifx_SDMMC_KRST1_Bits.RST */
#define IFX_SDMMC_KRST1_RST_LEN (1u)

/** \brief Mask for Ifx_SDMMC_KRST1_Bits.RST */
#define IFX_SDMMC_KRST1_RST_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_KRST1_Bits.RST */
#define IFX_SDMMC_KRST1_RST_OFF (0u)

/** \brief Length for Ifx_SDMMC_KRSTCLR_Bits.CLR */
#define IFX_SDMMC_KRSTCLR_CLR_LEN (1u)

/** \brief Mask for Ifx_SDMMC_KRSTCLR_Bits.CLR */
#define IFX_SDMMC_KRSTCLR_CLR_MSK (0x1u)

/** \brief Offset for Ifx_SDMMC_KRSTCLR_Bits.CLR */
#define IFX_SDMMC_KRSTCLR_CLR_OFF (0u)

/** \}  */

/******************************************************************************/

/******************************************************************************/

#endif /* IFXSDMMC_BF_H */
